---- From http://www.xbitlabs.com/articles/cpu/display/amd-k10_8.html

Load/Store Unit

When the memory request addresses have been calculated in the AGU of K8 processor, all load and store operations are sent to LSU (Load/Store Unit). LSU contains two queues: LS1 and LS2. At first, load and store operations get into LS1 queue 12 elements deep. At two operations per clock speed, LS1 queue issues requests to L1 cache memory in order determined by the program code. In case of a cache-miss, operations are placed into the LS2 queue 32 elements deep. This is where the requests to L2 cache memory and RAM come from.

The LSU of the K10 processor has been modified. Now LS1 queue receives only load operations, while store operations are sent to LS2 queue. Load operations from LS1 can be executed in an out-of-order manner taking into account addresses of store operations in LS2. As we have already mentioned above, K10 processes 128-bit store operations as two 64-bit ones that is why they take two positions each in the LS2 queue.

L1 Cache

L1 cache in K8 and K10 processors is separated: 64KB for instructions (L1I) and data (L1D). Each cache is 2-way set associative; the line length is 64 bytes. This low associativity may result into frequent conflicts between the lines aiming at the same sets, which in its turn may increase the number of cache-misses and negatively affect the performance. Low associativity is often compensated by the rather large size of L1 cache. A significant advantage of L1D is the two ports: it can process two read and/or write instructions per clock in any combination.

Unfortunately, L1 cache of K10 processor still has the same size and associativity. The only noticeable improvement is the read bus width increase. As we have said in the previous chapter, now the CPU can perform two 128-bit reads every clock cycle, which makes it much more efficient during SSE-data processing in local memory.

L2 Cache

Each core of the dual-core and quad-core K8 and K10 processors has its own individual L2 cache. The L2 cache in K10 remained the same: 512KB per core with associativity of 16. Exclusive L2 caches have their pros and cons compared with the shared L2 cache in Core 2 CPUs. Among the advantages, certainly are the absence of conflicts and competition for the cache when several processor cores are heavily loaded at the same time. As for the drawbacks, there is less cache available for each core when there is only one applications running full throttle.

L2 cache is exclusive: the data stored in L1 and L2 caches do not duplicate. L1 and L2 caches exchange data along two unidirectional buses: one serves to receive data and another one – to send data. In K8 processor each bus is 64bit (8 bytes) wide (Pic.5a). This organization provides the data delivery rate to L2 cache at the modest 8 bytes/clock speed. In other words, it will take 8 clock cycles to transfer a 64-bit line, so the data delivery to the core will be delayed noticeably, especially if two or more lines of the L2 cache are addressed at the same time.

Although it hasn’t been confirmed yet, the send and receive buses in K10 processor will become twice as wide, i.e. 128bit each (Pic.5b). It should reduce the cache access latency significantly when two or more lines are requested at the same time.

L3 Cache

To make up for the relatively small L2 cache, K10 acquired a shared between all cores 2MB L3 cache with associativity of 32. L3 cache is adaptive and exclusive: it stores all data evicted from L2 caches of all cores as well as the data shared by several cores. When the core issues a line read request, a special check is performed. If the line is only used by one core, it is removed from L3 freeing room for the line that is evicted from L2 cache of the requesting core. If the requested line is also used by another core, it remains in the cache. However, in order to accommodate the line evicted from L2 cache, another – older – line will be removed in this case.

L3 cache should help speed up the data transfer rate between the cores. As we have already found out, contemporary Athlon 64 processors exchange data between the cores via the memory bus. As a result, access to shared modified data occurs much slower. According to AMD’s materials, quad-core K10 processors may exchange data via L3 cache. Once the request from one of the cores arrives, the core that has the modified data copies them to L3 cache, where the requesting core can read them from. The access time to modified data in the other core’s cache should become much shorter. When we get a chance, we will certainly check it out.

Pic.6: Data transfer between the cores in K10 processors.

L3 cache latency will evidently be higher than L2 cache latency. However, AMD materials suggest that the latency will vary adaptively depending on the workload. If the workload isn’t too heavy, latency will improve, and under heavy workload the bandwidth will rise. We still have to check what really stands behind this.

TLB

Besides cache-memory for instructions and data, processors have one more type of cache-memory: translation-lookaside buffers (TLB). These buffers are used to store the connection between virtual and physical page addresses obtained from the page

tables. The number of TLB entries determines how many memory pages can be involved without additional costly page table walks. This is especially critical for applications that process memory data randomly, when they constantly request the data on different pages. K10 processor has much more translation buffers. For your convenience they are all given in the table below:

Table 1: TLB capacity of K8 and K10 processors.

As you see from the table, there are much more buffers for translation of 2MB pages. There also appeared support of large 1GB pages that may be very useful for servers processing large volumes of data. With appropriate support from OS, applications using large 2MB and 1GB pages should run considerably faster.

Memory Controller

When the requested data isn’t found in any of the caches, the request is issued to the memory controller integrated onto the processor die. On-die location of the memory controller reduces the latencies during work with the memory, but at the same time it ties up the processor to a specific memory type, increases the die size and complicates the die selection process thus affecting the production yields. The on-die memory controller was one of the advantages of the K8 processors, however, sometimes it wasn’t efficient enough. The memory controller of K10 processors will be improved significantly.

Firstly, it now can transfer data not only along one 128-bit channel, but also along two independent 64-bit channels. As a result, two or more processor cores can work more efficiently with the memory at the same time.

Secondly, the scheduling and reordering algorithms in the memory controller have been optimized. The memory controller groups reads and writes so that the memory bus could be utilized with maximum efficiency. Read operations have an advantage over writes. The data to be written is stored in the buffer of still unknown size (it is assumed to accommodate between 16 and 30 64-byte lines). By handling requested lines in groups we can avoid switching the memory bus from reading to writing and back all the time and thus save resources. It is allows to significantly improve performance during alternating read and write requests.

Thirdly, the memory controller can analyze requests sequences and perform prefetch.

Prefetch

Prefetch is a definite advantage of K8 processors. Integrated memory controller with low latency has let AMD processors to demonstrate excellent performance with the memory subsystem for a long time. However, K8 processors failed to prove as efficient with new DDR2 memory, unlike Core 2 with powerful prefetch mechanism. K8 processors have two prefetch units: one for the code and another one for the data. The data prefetch unit fetches data into the L2 cache basing on simplified successions.

K10 has improved prefetch mechanism.

First of all, k10 processors prefetch data directly into the L1 cache, which allows hiding the L2 cache latency when requesting data. Although it increases the probability of L1 cache pollution with unnecessary data, especially taking into account low cache associativity, AMD claims that it is a justified measure that pays off well.

Secondly, they implemented adaptive prefetch mechanism that changes the prefetch distance dynamically, so that the data could arrive in time and so that the cache wouldn’t get loaded with data that is not needed yet. Prefetch unit became more flexible: now it can trains on memory requests at any addresses, and not only the addresses that fall into adjacent lines. Moreover, prefetch unit now trains on software prefetch requests.

Thirdly, a separate prefetch unit was added directly into the memory controller. The memory controller analyzes request successions from cores and loads the data into the write buffer utilizing the memory bus in the most optimal way. Saving prefetch lines in the write buffer helps keep cache-memory clean and reduce the data access latency significantly.

As a result, we see that the memory subsystem of K10 processors has undergone some positive improvements. But we still have to say that it still potentially yields to the memory subsystem in Intel processors in some characteristics. Among these features are: the absence of speculative loading at unknown address past the write operations, lower L1D cache associativity, narrower bus between L1 and L2 caches (in terms of data transfer rate), smaller L2 cache and simpler prefetch. Despite all the improvements, Core 2 prefetch is potentially more powerful than K10 prefetch. For example, K10 has no prefetch at instruction addresses so that we could keeps track of individual instructions, as well as no prefetch from L2 to L1 that could hide L2 latency efficiently enough. These factors can have different effects on various applications, but in most cases they will determine higher performance of Intel processors.

AMD is working on a way to make a multi-core processor appear to the host operating system as a single-core chip, it has been claimed. If true, the move turns on its head the drive to develop multi-threaded apps the better to take advantage of multiple cores.

The technology is aimed at the next architecture after K8, according to a purported company mole cited (http://www.x86-secret.com/?option=newsd&nid=933) by French-language site x86 Secret. It's well known that two CPUs - whether two separate processors or two cores on the same die - don't generate, clock for clock, double the performance of a single CPU. However, by making the CPU once again appear as a single logical processor, AMD is claimed to believe it may be able to double the single-chip performance with a two-core chip or provide quadruple the performance with a quad-core processor.

Clovertown, a four-core processor, will start shipping to computer manufacturers late this year and hit the market in early 2007. Clovertown will be made for dual-processor servers, which means that these servers will essentially be eight-processor servers (two processors x four cores each).

Core expansion will be a dominant theme for Intel over the next few years, said Chief Technology Officer Justin Rattner. By the end of the decade, chips with tens of cores will be possible, while in 10 years, it's theoretically possible that chips with hundreds of cores will come out, he added.

Multiplying the number of cores brings distinct advantages. First, it cuts down overall energy consumption for equivalent levels of performance. If the recent Core Duo chips released for notebooks from Intel had only one core, the chips would consume far more power, he said.

Integrating processor cores into the same piece of silicon or same processor package also increases performance by reducing the data pathways

"To go from core to core can be a matter of nanoseconds," Rattner said. "As soon as you move cores together you get an automatic improvement in available bandwidth."

Nonetheless, adding cores requires careful planning. Energy efficiency, data input/output and memory latency (the time it takes data to go from memory and the processor and vice versa) will be major issues with each level of core expansion.

To get around some of these issues, Intel is conducting research into circuit design and chip architecture as it has in the past. In addition, the company is working with application developers to determine how the architecture of its chips can be optimized.

By working with one server application developer, Intel determined that it needed to make three small changes to the architecture of one of its future server chips. Before the changes, the application only ran well in simulations on chips with 16 cores. After that, performance began to decline, Rattner said.

After the changes, performance continued to climb. "We got it to scale well past 32" cores, he said.

Another pending change to chip design to accommodate problems that arise with core multiplication are Through Silicon Vias, or TSVs. With TSVs, processors and memory chips are stacked up and connected through tiny wires; the top of one chip wires directly into the bottom of another. Currently, chips connect through buses, long data paths that have become as crowded as rush-hour freeways in some computers.

Clovertown and Tigerton are members of a new chip architecture coming from Intel at the end of the year. A notebook chip called Merom and a desktop chip called Conroe coming out around the same time will be based on the same architecture. Intel will give the architecture a name at the Intel Developer Forum taking place in March.

"The core growth on the client side will be slower than on the server side," he said. The new chip architecture "is intended for dual and multiple core architectures," he added.

Rattner would not state whether Tigerton and Clovertown contained a single piece of silicon, or two pieces of silicon in a single package. A processor is made of silicon and the package that surrounds it, so either definition could fit.

Two pieces of silicon in a single package seems more likely. At around the same time, after all, Intel will release Woodcrest, a dual core server chip based around the same Merom-Conroe-Tigerton-Clovertown architecture. It will contain only two cores and consume 80 watts of power, less than the 165-watt server chips Intel sells now.

Intel has already released one dual core processor that contained two pieces of silicon. While using two pieces of silicon can be cheaper to design and manufacture, some have said dual silicon chips don't provide the same level of performance.